1. Field of the Invention
The present invention relates to an apparatus and method for packaging critical chips used in high speed applications. More specifically, the present invention relates to an integrated circuit package and packaging technique which would minimize interconnection distances between at least two critical chips, such as, for example, a central processing unit "CPU") chip and an external cache memory chip, as well as reduce the total footprint area (i.e., the surface area used by the associated chip packages and corresponding connections) of the integrated circuit package implemented on the substrate board.
2. Background of the Field
Over the last decade, there have been many advances in integrated circuit technology which have had a dramatic impact on the computer industry. Each and every year, computer companies are providing faster and more sophisticated computer systems. These computer systems are, of course, designed and built with faster and more sophisticated critical chips. For the purpose of this application, critical chips are defined as chips that are necessary for the computer system to function properly, such as, for example, CPUs, memory chips, etc.
It is common knowledge that critical chips, especially CPU chips, are constantly being designed with a greater number of additional features and with the capability of supporting such additional features. Current generation CPU chips are now being implemented into integrated circuit packages having large lead counts in a range of a couple hundreds of output leads (i.e., pins). For example, one of Sun's Microsystems' microprocessor products has 288 pins with a pitch (i.e., the spacing distance between the pins) of approximately 0.25 millimeters. With the advent of more advanced critical chips, a greater lead count will be required.
One problem associated with increasing lead count is that the pitch between pins drastically decreases, provided the same total footprint area is desired. Finer pitch has a direct result in increasing manufacturing costs for two primary reasons. A first reason being that it is more likely that the leads will not be positioned properly by the assembly machines because there now exists a smaller degree of error in placement of the leads by the assembly machines. As a result, yield losses increase resulting in an increase in component costs. The second reason being that more precise assembly machinery may be required in order to satisfy the finer pitch requirements, thereby requiring a large increase in capital investment.
A second problem occurring in the next generation of critical chips is that as performance goes up, propagation time delays play a greater role in computer operations. It is known that there exists a propagation time delay for data to travel between a first and a second critical chip. As these critical chips are designed to operate at greater frequencies, the delay caused by the interconnection distances between such chips plays a paramount role in the overall speed of the computer system. Thus, there is a need for a package and packaging technique to reduce such time delays.
Another problem coming into view with respect to next generation critical chips is greater thermal dissipation will be required. Tape Automated Bonding ("TAB"), Quad Flat Package ("QFP") type packages are not easy packages to modify when the chip is dissipating over 20 watts. Therefore, the public is desirous of obtaining an alternate package that provides sufficient thermal dissipation without complex package modifications.